The present invention relates to a multi-screen display system wherein a plurality of projector units are distributed in a matrix arrangement.
FIG. 2 shows a general arrangement for a multi-screen display system wherein a signal source 1 supplies a signal to a multiprocessor 2 which provides respective output signals to a multi-screen display 3. The multi-screen display includes two columns and two rows wherein 1-1, 1-2, . . . etc. are the display units of the first row and the first column, the first row and the second column, . . . etc. respectively, and correspond to output signals D.sub.1-1, D.sub.1-2, ... from the multiprocessor. FIG. 3 shows the construction of a display unit including a CRT 4 for projection, a lens 5 for projection, and a screen 6.
FIG. 4 is a block diagram arrangement of a conventional multiprocessor 2 wherein VD.sub.i, HD.sub.i and D.sub.i represent an input vertical synchronous signal, an input horizontal synchronous signal and an input picture signal, respectively. There is provided a phase detector 7, a voltage control oscillator 8 (hereinafter abbreviated as "VCO"), and a programmable counter 9 for generating a horizontal address (X) which form a well-known PLL (Phase Lock Loop). As an example, the vertical/horizontal scanning frequency of the input signal is approximately 60 Hz/32 KHz, the number of total scanning lines is approximately 500 lines, and the oscillation frequency for the VCO is approximately 30 MHz. A programmable counter 10 serves for generating a vertical address (Y) and counts the number of output horizontal synchronous pulses (HD.sub.0) and is reset by the vertical synchronous signal VD.sub.i. An AD converter 11 is coupled to an SP converter for converting serial signals into parallel signals. There is also provided a frame memory 13 wherein M.sub.1-1 is a memory for the first row of the first column, M.sub.1-2 is a memory for the first row of the second column, M.sub.2-1 is a memory for the second row of the first columns and M.sub.2-2 is a memory for the second row of the second column, each being composed of a first memory and a second memory. A line memory 14 is coupled to the frame memory.
FIGS. 5A and 5B show the principle of the operation of the multiprocessor of FIG. 4 wherein a timing chart 15 is shown in FIG. 5A and the abscissa t indicates time marked in a frame unit while the ordinate indicates a memory address. M.sub.1-1, 1 is the first memory for the first row and the first column, M.sub.2-1, 1 is the first memory for the second row and the first column, M.sub.1-1, 2 is the second memory for the first row and the first column, and M.sub.2-1, 2 is the second memory for the second row and the first column, and correspond to the frame memory 13 in FIG. 4. Memories corresponding to the second column are omitted in FIG. 5A. In the figure, for example, W3 indicates that picture signals of the frame 3 are written into the memory. R.sub.3 indicates that picture signals of the frame 3 are read out from the memory. Output signals being read out pass through the line memory 14 in FIG. 4, and are outputted as D.sub.1-1, D.sub.2-1, and are supplied to the multi screen display 3 in FIG. 2. In the prior art, vertical/horizontal scanning frequencies of the multi screen display 3 are approximately 60 Hz/32 kHz like those of the input signals. The total number of the scanning lines for the input signals is approximately 500 and are divided into 250 lines for the upper stage (for the first row) and 250 lines for the lower stage (for the second row) and are written into frame memories M.sub.1-* and M.sub.2-*, respectively, and are read out concurrently at the timing indicated in FIG. 5A. The line memory 14 is used for outputting picture signals corresponding to the same scanning line two times repeatedly.
In the prior art, however, there is a defect that discontinuity interference and inclination distortion of moving pole images take place as indicated in 16 of FIG. 5B wherein the moving pole image is a vertically extending image moving horizontally across the rows of the display screen. In FIG. 5B, a rectangular frame 16-1 is a frame for the whole screen. A discontinuous slanting line 16-2 is a vertical moving pole image. That is, although the original vertical pole is to be moved at the speed v to the right side, a distorted pole is seen as indicated in 16-2 in the figure for the first and second rows. This phenomenon is explained quantitatively below. Making the discontinuity width .DELTA.x, this is equal to approximately v.DELTA.t, where .DELTA.t is a time difference described as indicated in FIG. 5A, and is equal to vertical scanning period of approximately 15 ms. Accordingly, in the case of a body moving at approximately 15 mm/15 ms (1 m/s), the discontinuity of approximately 15 mm has been produced at the link or boundary of the upper/lower rows of the screen (This is referred to as a discontinuity interference). Moreover, in FIG. 5A, since the speed in writing the picture signals into the memory (gradient of the solid lines indicating the writing-in speed) is different from the speed in reading out the signals from the memory (gradient of the dotted lines indicating the reading-out speed), the moving pole which is originally vertical is inclined by an angle .theta.=.DELTA.x/H (where H is a height of screen) (this is denominated as inclination distortion).
FIG. 6A shows a timing chart 17 and FIG. 6B shows a moving pole distortion 18 in the case of four rows and four columns in accordance with the prior art.
FIG. 7 shows a timing chart 19 for an improved example according to the prior art as described in Japanese Patent Application Laid-Open No. 3-114373 having a laid-open date of May 15, 1991, and FIG. 7B shows a moving pole distortion 20 in the case for four rows and four columns wherein four sets of the frame memories 13 in FIG. 4 are used. As is apparent from FIG. 7B, the discontinuity interference at the links of the rows of screens is eliminated, but there is a problem that the inclination distortion remains. Moreover, there is also a problem that many sets of frame memories are required.